Cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation

ABSTRACT

A method and system are provided for forward error correction. Embodiments of the present disclosure provide a strong FEC algorithm that performs similarly to RS(255,239) when a simple decoder is used, and scales up linearly to a full-scale decoder that outperforms all 7% algorithms currently in G.975.1. The Forward Error Correction code is suitable for use in optical transport networks (OTN) and other applications requiring high decode performance and high code rate. Embodiments of the present disclosure provide an FEC code that is a cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority of U.S. ProvisionalPatent Application No. 61/158,646 filed Mar. 9, 2009, which isincorporated herein by reference in its entirety.

FIELD

The present disclosure relates generally to error correction. Moreparticularly, the present disclosure relates to high code-rate forwarderror correction codes for optical and high performance applications.

BACKGROUND

Two-dimensional concatenated block codes are widely used at 10 G, forexample those defined in annexes I.4, I.7, and I.9 of ITU-T G.975.1.FIG. 1 shows a generic 2-D code, in which every bit is covered by twoblock codes. Decoding proceeds by correcting each row, then each column,and iterating. This is an excellent strategy, but each row is coveredonly by the columns, and each column only by the rows.

As data rates have risen to 40 G and 1000, a forward error correction(FEC) stronger than the standard RS(255,239) has become necessary on amajority of links. At 10 G and 40 G, this has resulted in theimplementation of a variety of strong, proprietary Intra DomainInterface (IaDI) FECs that do not interoperate.

It is, therefore, desirable to provide an improved FEC.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure will now be described, by way ofexample only, with reference to the attached Figures, wherein:

FIG. 1 illustrates a generic 2-D code, in which every bit is covered bytwo block codes.

FIG. 2 illustrates an example implementation of a module/framerinterface according to an embodiment of the present disclosure.

FIG. 3 illustrates a message block and some steps in a method ofcodeword construction according to an embodiment of the presentdisclosure.

FIG. 4 illustrates a codeword and intermediate elements in a method ofcodeword construction according to an embodiment of the presentdisclosure.

FIG. 5 illustrates a codeword array construction according to anembodiment of the present disclosure.

FIG. 6 illustrates a parity-on-parity construction according to anembodiment of the present disclosure.

FIG. 7 is a flowchart illustrating an encoding procedure according to anembodiment of the present disclosure.

FIG. 8 is a flowchart illustrating a decoding procedure according to anembodiment of the present disclosure.

FIG. 9 is a graph illustrating performance of an FEC according to anembodiment of the present disclosure.

DETAILED DESCRIPTION

It is an object of the present disclosure to obviate or mitigate atleast one disadvantage of previous error correction code approaches.

According to an aspect, there is provided a method of constructing acodeword in a forward error correction system having K information bitsin a total of N bits. The method comprises obtaining K/2 home columninformation bits from a home column of an information bit array;obtaining K/2 away column information bits from a selected number ofaway columns of the information bit array, the selected number of awaycolumns consisting of information bit array columns other than the homecolumn; combining the K/2 home column information bits with the K/2 awaycolumn information bits to assemble K information bits; calculating N−Kredundant parity bits associated with the assembled K information bitsaccording to an error control code; and appending the N−K redundantparity bits to the assembled K information bits to assemble the codewordvalid under the error control code.

The method can also include prepending padding bits, for example, nullbits or zero bits, to the assembled K information bits.

The K/2 home column information bits and the K/2 away column informationbits can be combined in an alternating manner to assemble the Kinformation bits.

The K/2 away column information bits can be obtained by following adiagonal progression through the selected number of away columns thatskips the home column. The K/2 away column information bits can also beobtained by following a diagonal progression through the selected numberof away columns that skips the home column and one or more columnsadjacent to the home column. The K/2 away column information bits can beobtained beginning at a first away column adjacent the home column.

In an embodiment, the K/2 home column information bits and the K/2 awaycolumn information bits are combined by interleaving the K/2 home columninformation bits and the K/2 away column information bits to assemblethe K information bits.

The error control code can be a BCH (Bose, Chaudhuri, and Hocquenghem)code. The method for forward error correction can be performed byinterleaving large-block BCH codes, decoding them all at once, and usingconfidence levels to reconcile the decoder outputs. Every informationbit can be covered by at least two codewords, and such that everycodeword shares bits with every other codeword.

The above method can be implemented in an apparatus for forward errorcorrection having means for interleaving large-block BCH codes, meansfor decoding them all at once, and means for using confidence levels toreconcile the decoder outputs.

In an aspect, there is an encoding procedure comprising constructing aninformation bit array by placing information bits into the informationbit array; constructing W codewords, each N bits long, with null parityand zero padding; calculating T*M bits of BCH parity for each codeword,and inserting the calculated parity bits into a message block;constructing parity codewords, and calculating the parity on parityarray; adding framing by generating frames; and transmitting the messageblock with the generated frames.

The information bit array can be constructed by sequentially assigning arow and column address to each incoming data bit. The codewords can beconstructed using a programmable shift register to perform theinterleaving function as an interleaver in order to construct thecodewords as described above.

The hardware for BCH encoding may be implemented as a convenient numberof BCH encoders, each capable of handling one or more BCH codewords in atime-interleaved fashion. The parity bits can be inserted into eachcodeword by writing them into the appropriate position in a memory. TheBCH parity can be formed into new codewords, and the parity on paritycan be calculated using the BCH parity by the aforementioned method. Theparity on parity bits can be inserted into the message block by writingthem into the appropriate position in a memory. Any desired framing (forinstance, G.709 FAS and MFAS, plus a pointer indicating the current rowand column position within the message block) can be added and themessage block can be transmitted.

In an aspect, there is provided a method of decoding an encoded bitstream having encoded information bits, encoded parity bits and encodedparity-on-parity bits. The method comprises assembling informationcodewords from the encoded information bits and the encoded parity bits;assembling parity codewords from the encoded parity bits and the encodedparity-on-parity bits; decoding the information codewords and the paritycodewords to provide decoded information codewords, decoded paritycodewords and associated per-codeword confidence metric for each of thedecoded information codewords and for each of the decoded paritycodewords. For each information bit to be decoded, each information bitbeing associated with two decoded information codewords, the methodcomprises obtaining the decoded information bit based on one of the twodecoded information codeword having a higher per-codeword confidencemetric.

Each parity bit to be decoded can have one corresponding decodedinformation codeword and one decoded parity codeword. Each decodedparity codeword can have a corresponding error mask and a correspondingerror count. For each parity bit to be decoded, the corresponding errorcodes and the corresponding error counts of the corresponding decodedinformation codeword and decoded parity codeword can be reconciled toidentify a reconciled parity codeword having a higher per-codewordconfidence metric.

The per-codeword confidence metric can be determined by determining anerror count for each of the decoded information codewords and thedecoded parity codewords. The per-codeword confidence metric can bedetermined by determining a correctability flag for each decodedinformation codewords and for each of the decoded parity codewords. Thecorrectability flag can be encoded as a particular value of the errorcount or a particular value of a confidence metric for each of thedecoded information codewords and the decoded parity codewords. Each ofthe decoded information codewords and the decoded parity codewords isassociated with an error mask.

A default error mask and a default error count can be assigned for eachof the decoded information codewords and the decoded parity codewordsthat are uncorrectable.

Each of the decoded information codeword can have a corresponding errormask and a corresponding error count. For each information bit to bedecoded, the corresponding error codes and the corresponding errorcounts of the two corresponding decoded information codewords can bereconciled to identify a reconciled information codeword having thehigher per-codeword confidence metric.

The error mask of the reconciled information codeword and the error maskof the reconciled parity codeword can be applied on the reconciledinformation codeword and the reconciled parity codeword respectively toobtain the decoded information bit and the decoded parity bit,respectively.

The reconciled information codeword can be determined based comparingthe two error counts of the two corresponding decoded informationcodewords. The reconciled party codeword can be compared based comparingthe two error counts of the two corresponding decoded parity codewords.

In an aspect, there is provided an encoder comprising an information bitarray assembly module and a codeword assembly module. The informationbit array assembly module assembles information bits into an informationbit array. The codeword assembly module assembles a codeword in aforward error correction system having K information bits in a total onN bits by obtaining K/2 home column information bits form a home columnof the information bit array; obtaining K/2 away column information bitsfrom a selected number of away columns of the information bit array, theselected number of away columns consisting of information bit arraycolumns other than the home column; combining the K/2 home columninformation bits with the K/2 away column information bits to assemble Kinformation bits; calculating N−K redundant parity bits associated withthe assembled K information bits according to an error control code; andappending the N−K redundant parity bits to the assembled K informationbits to assemble the codeword valid under the error control code.

The codeword assembly module can prepend padding bits, for example, zeroor null bits, to the assembled K information bits. The K/2 home columninformation bits and the K/2 away column information bits can becombined in an alternating manner to assemble the K information bits.

The codeword assembly module can include a plurality of programmableshift registers to store the information bits during assembly of thecodeword. The plurality of programmable shift registers interleave theK/2 home column information bits and the K/2 away column informationbits to assemble the K information bits.

The encoder can further include a codeword assembly module; a parity bitarray assembly module and a parity on parity array assembly module. Thecodeword assembly module assembles a plurality of codewords associatedwith the information bits into a codeword array. The parity bit arrayassembly module assembles N−K redundant parity bits into a parity bitarray. The parity on parity array assembly module assembles parity onparity bits into a parity on parity bit array. The parity on parity bitscan be associated with the N−K redundant parity bits.

The encoder can also include a framing module for combing the codewordarray, the parity bit array, and the parity on parity array into anencoded message block.

In another aspect, there is provided a decoder for decoding an encodedbit stream having encoded information bits, encoded parity bits andencoded parity on parity bits. The decoder comprises an informationcodeword assembly module; a parity codeword assembly module; a codeworddecoding module; and an information bit decoding module. The informationcodeword assembly module assembles information codewords from theencoded information bits and the encoded parity bits. The paritycodeword assembly module assembles parity codewords from the encodedparity bits and the encoded parity-on-parity bits. The codeword decodingmodule decodes information codewords and parity codewords to providedecoded information codewords and decoded parity codewords andassociated per-codeword confidence metric for each of the decodedinformation codewords and for each of the decoded parity codewords. Theinformation bit decoding module decodes each information bit of theencoded bit stream, each information bit being associated with twodecoded information codewords, by obtaining the decoded information bitbased on one of the two decoded information codeword having a higherper-codeword confidence metric.

The decoder can further comprise a parity bit decoding module fordecoding each parity bit of the encoded bit stream, each parity bitbeing associated with one decoded information codeword and one decodedparity codewords, by obtaining the decoded parity bit based on one ofthe decoded information codeword and the decoded parity codeword havinga higher per-codeword confidence metric.

In another aspect there is provided an encoder comprising an informationbit array assembly module; a information codeword array assembly module;a parity bit array assembly module; a parity codeword array assemblymodule; a parity on parity array assembly module and a framing module.The information bit array assembly module assembles information bitsinto an information bit array. The information codeword array assemblymodule assembles a plurality of information codewords associated withthe information bits into an information codeword array, eachinformation bit being associated with two information codewords. Theparity bit array assembly module assembles parity bits into a parity bitarray, the parity bits associated with the plurality of informationcodewords according to an error control code. The parity codeword arrayassembly module assembles a plurality of parity codewords associatedwith the information bits into a parity codeword array. The parity onparity array assembly module assembles parity on parity bits into aparity on parity bit array, the parity on parity bits being associatedwith the parity bits according to the error control code. The framingmodule combines the information codeword array, the parity codewordarray, and the parity on parity array into an encoded message block.

In another aspect there is provided a method for encoding comprising:assembling information bits into an information bit array; assembling aplurality of information codewords associated with the information bitsinto an information codeword array, each information bit beingassociated with two information codewords; assembling parity bits into aparity bit array, the parity bits associated with the plurality ofinformation codewords; assembling a plurality of parity codewordsassociated with the information bits into a parity codeword array; andassembling parity on parity bits into a parity on parity bit array, theparity on parity bits being associated with the parity bits. The methodfor encoding can further include combining the information codewordarray, the parity codeword array, and the parity on parity array into anencoded message block.

In the interest of increased interoperability, it is desirable tospecify a 0.937 rate FEC that is suitable for both Inter DomainInterface (IrDI) and metro IaDI applications.

Embodiments of the present disclosure provide an approach, adapted fromlow density parity check (LDPC), whereby every block code covers everyother block code, thus maximizing the redundancy that can be applied toerror patterns.

Other aspects and features of the present disclosure will becomeapparent to those ordinarily skilled in the art upon review of thefollowing description of specific embodiments of the disclosure inconjunction with the accompanying figures.

Generally, the present disclosure provides a method and system forforward error correction. For IrDI applications, it is important thatthe implementation be relatively compact, low power, and low latency.For Metro/Regional IaDI applications, coding gain is very important,while higher latency and power are acceptable.

Embodiments of the present disclosure provide a strong FEC algorithmthat performs similarly to RS(255,239) when a simple decoder is used,and scales up linearly to a full-scale decoder that outperforms all 7%algorithms currently in G.975.1. The Forward Error Correction code usedin such embodiments is suitable for use in optical transport networks(OTN) and other applications requiring high decode performance and highcode rate. Embodiments of the present disclosure provide an FEC codethat is a cyclically interleaved dual BCH, with simultaneous decode andper-codeword maximum likelihood reconciliation.

FIG. 2 illustrates an example implementation of a module/framerinterface according to an embodiment of the present disclosure. FIG. 2illustrates an exemplary context in which embodiments of the presentdisclosure can be implemented. This embodiment provides a Forward ErrorCorrection code suitable for use in optical transport networks (OTN) andother applications requiring high decode performance (e.g. 9 dB netcoding gain at 1E-15 output bit error rate) and high code rate (e.g.R=239/255 for OTN).

Embodiments of the present disclosure draw elements from LDPC and fromthe 2-D codes in ITU G.975.1, and combines them in a novel way. Thereare 2-Dimensional and 3-Dimensional FECs (e.g. ITU-T G.975.1 AnnexesI.4, I.7, I.9) that use two or more concatenated block codes (RS and/orBCH) with iterative decode. There are 2-D codes (e.g. ITU-T G.975.1Annex I.7, and most ‘turbo’ codes) whose dimensions are chosen so thatno two codewords share more than X bits, where X<T for one or more ofthe component codes. There are codes (ITU-T G.975.1 Annex I.9) that aredesigned to have an erasure-decoding step at the end. LDPC techniquescompute all the redundant information at once, and use bitwiseconfidence measures to resolve between them.

Embodiments of the present disclosure are unique in the way theyinterleave large-block BCH codes, decode them all at once, and useconfidence levels to combine them. Like a 2-D code, every bit in a codeaccording to an embodiment of the present disclosure is covered byexactly two codewords. However, simultaneous decode of all codewords atonce allows for twice as many iterations for the same latency/memory asa 2D code. Per-codeword confidence metrics reduce the impact of falsecorrection compared with existing 2D codes, without the very highimplementation cost of a true ‘soft’ decode. Use of large BCH blocksallows for excellent performance at low overhead (7%) compared withLDPC.

Embodiments of the present disclosure provide an FEC code that is acyclically interleaved dual BCH, with simultaneous decode andper-codeword maximum likelihood reconciliation. For conciseness, thiswill be referred to as a “Swizzle” code hereinafter. Further details ona particular embodiment will now be provided.

The base component code is a shortened BCH (N,K,T). One instance of thisBCH (K message bits, N−K=T*M parity bits, and Z=2^(M)−N−1 prependedzeroes) is a Codeword, where error correction capability is T bits, andM is the order of the BCH. M is roundup(log 2(N)). Padding length Z is2^(M)−N−1.

A group of codewords, intended to be decoded iteratively as a group, area Code Block. A Code Block is an array N bits high by W bits wide.

FIG. 3 illustrates a message block and steps in a method of codewordconstruction according to an embodiment of the present disclosure. Themessage bits, or uncoded information bits, can be arranged into amessage array shown in FIG. 3 as an information bit array 110 that isK/2 bits high, and W bits wide, where W is the number of interleavedcodewords in a block. W can be chosen to be large enough to minimize thechance that two codewords interleave in such a way that both areuncorrectable, for example that (K/2W)=<T−1.

A codeword w includes the K/2 bits in information array column w (fromamong the columns W), plus an additional K/2 message bits selected bythe Interleaver from other columns, plus T*M parity bits, plussufficient zeros to pad out the codeword to 2^(M)−1 bits. Calculatingthe parity bits associated with the assembled codewords yields a ParityArray 112 that is W bits wide and T*M bits high.

Stacking the information bit array 110 with the parity array 112, andappending a Parity-on-Parity array 114, yields the N×W Message Block116. The Information Bit Array 110, the Parity Bit Array 102 calculatedfrom the codewords, and the Parity-On-Parity Array 114 together form theMessage Block 116 that is transmitted. Framing information, or framing,(not shown in FIG. 3) for instance OTN framing plus MFAS, once perframe, is added, and transmitted by reading left-to-right,top-to-bottom. In embodiments, the Message Block plus framing is what isactually transmitted.

Performance data can be provided for a Message Block using parametersN=1761, K=1706, T=5, and W=352, according to an embodiment of thepresent disclosure.

A basic property of an interleaving strategy according to an embodimentof the present disclosure is that every information bit be covered Dtimes. In an exemplary embodiment, a value of D=2, according to whichevery information bit is covered exactly twice, yields a desiredperformance.

An method of constructing a codeword according to an embodiment of thepresent disclosure can be described as follows, and in relation toreference numerals 120, 122 and 124 (currently 1, 2 and 3) in FIG. 3.FIG. 4 illustrates a codeword and intermediate elements in a method ofcodeword construction according to an embodiment of the presentdisclosure.

In step 120, a codeword 130 (shown in FIG. 4) is constructed out of K/2information bits from a single column, known as the ‘home’ column 122,alternating with K/2 bits from other columns, or away columns 124,following a diagonal progression shown in steps 126 that skip the ‘home’column in each row.

A shortened codeword array C, also shown in FIG. 5 as 134, can bedefined, which is N high and W wide. c(k_(c),w_(c)) is an element of C.The information bit array A, also illustrated as 110, is defined, whichis K/2 high by W wide. a(k_(a),w_(a)) is the element of A such thatc(k_(c),w_(c))=a(k_(a),w_(a)).

The first K bits of the codeword 130 shown in FIG. 4 can be constructedusing these equations:

$\begin{matrix}{k_{a} = {{{ceiling}\mspace{14mu}( {k_{c}/2} )\mspace{14mu}{for}\mspace{14mu} 1}<=k_{c}<=K}} & \; \\{w_{a} = w_{c}} & {{{{for}\mspace{14mu} 1}<=w_{c}<=W},{k_{c}\mspace{14mu}{odd}}} \\{w_{a} = \{ \lbrack {w_{c} + k_{a} + {{floor}( ( {k_{a} -}  }}  } & {{{{for}\mspace{14mu} 1}<=w_{c}<=W},{k_{c}\mspace{14mu}{even}}} \\{ { { { 1 )/( {W - 1} )} ) + 1} \rbrack{mod}\; W} \} + 1.} & \;\end{matrix}$

The BCH parity bits are calculated over each BCH codeword. Parity bits128 shown in FIG. 3 are parity bits which are generated based on, orassociated with, the codewords. The resulting N−K*W parity bits areplaced in the parity array P, also shown as 112, p(i, w)=c(K+i, w) for1<=i<=N−K, 1<=w<=W.

In order to doubly cover the parity bits, each parity bit is also amember of a Parity Codeword. Each Parity Codeword is assembled byconcatenating a convenient number of bits from the Parity Array, withthe requirement that no more that T−1 bits from any column may bemembers of the same Parity Codeword.

FIG. 5 illustrates a codeword array construction according to anembodiment of the present disclosure. FIG. 5 illustrates a codewordarray 132 assembled from a plurality of codewords 130 as described inrelation to FIG. 4. FIG. 5 also illustrates a shortened codeword array134 which omits the prepended padding bits as compared to the codewordarray 132, and includes the parity bit array 112.

The codeword array comprises W BCH codewords derived from theinformation bits, and an additional P codewords derived from the paritybits. Each of the W codewords contains K/2 bits from one column, and anadditional K/2 bits from the remaining columns.

The choice of M, which is the order of the BCH code, determines thecomplexity of the decode blocks.

In an embodiment, it is desirable to have T to be as large aspracticable. T=Floor (2^M*(1−R)/2M).

Choose (N,K) such that it satisfiesN−K=T*MK/N>=R

Then, choose W such that no two codewords share more than T bits (or,preferably, T−1 bits). This is done by setting K/2W<=T−1. The limits onthis parameter are latency and memory.

The size of the Message Array is W*(K/2+(N−K)+N(N−K)/K)

In an embodiment, a parameter set, for a FEC with R=0.937 is: N=1761,T=5, and W=352.

FIG. 6 illustrates a parity-on-parity construction according to anembodiment of the present disclosure, in relation to a parity codewordarray 136. In an embodiment, Mp, Np, Kp, Tp, Wp can be selected for theParity on Parity array 114. A parity codeword 138 is constructed byrearranging the contents of the parity bit array 112 into a codeword,for example by sequentially traversing parity bit array 112 from left toright, top to bottom, filling each of the P parity on parity codewordsequally as shown in FIG. 5. These should be chosen similar to M, N, K, Tto balance the protection. However, these parameters may be chosen morefor convenience than optimal performance.

FIG. 7 is a flowchart illustrating an encoding procedure according to anembodiment of the present disclosure. In an embodiment, the encodingprocedure of FIG. 7 can be described as including the following steps:place information bits into information bit array and construct theinformation bit array (step 140); construct W codewords, each N bitslong, with null parity and zero padding (step 142); calculate T*M bitsof BCH parity for each codeword, and insert parity into message block(step 144); construct parity codewords, and calculate the parity onparity array (step 146); add framing by generating frames (step 148);and transmit (step 150).

In one embodiment, an apparatus for forward error correction isprovided, which performs the method shown in FIG. 7. The apparatus canbe implemented using standard logic gates and memories in an integratedcircuit, Field-programmable gate array, or similar technology (a‘hardware’ embodiment).

One embodiment of the present disclosure can be described as followsdescribing method steps in relation to associated hardware. Constructthe Information bit array by sequentially assigning a row and columnaddress to each incoming data bit. Construct the codewords using aprogrammable shift register to perform the interleaving function as aninterleaver in order to construct the codewords as described above.Calculate BCH parity for the codewords using BCH encoding. Those ofordinary skill in the art will be familiar with steps used for suchcalculation. The hardware for BCH encoding may be implemented as aconvenient number of BCH encoders, each capable of handling one or moreBCH codewords in a time-interleaved fashion. Insert the parity bits intoeach codeword by writing them into the appropriate position in a memory.Form the BCH parity into new codewords, and calculate the ‘Parity onParity’ by calculating BCH parity on them by the aforementioned method.Insert the ‘Parity on Parity’ bits into the message block by writingthem into the appropriate position in a memory. Add any desired framing(for instance, G.709 FAS and MFAS, plus a pointer indicating the currentrow and column position within the message block) and transmit.

In other embodiments, the method in FIG. 7 may be implemented usingsoftware instructions executed in a microprocessor, or a blend of‘hardware’ and software.

FIG. 8 is a flowchart illustrating a decoding procedure according to anembodiment of the present disclosure. FIG. 8 demonstrates the baselinedecoding procedure. Individual implementations can choose the exactdecoder, including the number of iterations.

In an embodiment, the decoding procedure of FIG. 8 can be described asincluding the following steps: assemble W codewords from the informationand parity bits (step 152); assemble parity (P) codewords from theparity and parity-on-parity bits (step 154); decode all codewordssimultaneously (step 156). Step 156 can produce an error mask and errorcount for each codeword, uncorrectable codewords use Mask=0, count=T+1.For each bit in the message, find the two codewords that cover it andreconcile (step 158) their error masks, for example as follows: if theerror masks agree, no dispute; otherwise, use mask from codeword withlowest number of corrected bits; repeat for the desired number ofstages, or until no further errors are being corrected. A final step(not shown), which can be implemented, is: determine if there are 3 orless uncorrectable BCH. If there are, use an erasure-based BCH decodetechnique to correct this pattern.

On reception, in step 152 the W codewords are recreated from thereceived stream by rebuilding the set of codewords from the receivedblock (including adding in the padding zeroes).

Each BCH codeword is then independently decoded in step 156. An errormask, count of corrections, and an uncorrectable indication aregenerated for each codeword. These, plus the received codeword values,are sent to the Reconciliation block for performing step 158.

With respect to step 158, each message bit, or information bit, is amember of two information codewords, Ca and Cb. The BCH decoder providesan error mask (error mask a for Ca, and error mask b for Cb). A count ofthe errors detected in each codeword is also provided, along with anindication of whether it is correctable. Confidence in a given codewordis determined by the number of bit errors each one is reporting, and canbe stored as a per-codeword confidence metric. Where an informationcodeword is uncorrectable, its error mask is considered all-zeroes, andits # errors=T+1.

Table 1 illustrates error mask reconciliation according to an embodimentof the present disclosure. The rationale for the reconciliation step isthat, when a codeword is falsely corrected, it is much more likely toreport a high number of bits corrected (usually T bits). Thus the numberof bits corrected is a measure of confidence in the correctness of thedecoding, with lower numbers being better.

TABLE 1 Error Mask Reconciliation #errors for C_(a) < Post-Vote errormask a error mask b #errors for C_(b)? Mask Comment 0 0 n/a 0 No dispute1 0 Yes 1 c_(a) wins 0 1 Yes 0 c_(a) wins 1 0 No 0 c_(b) wins 0 1 No 1c_(b) wins 1 1 n/a 1 No dispute

Note that only W confidence values, or per-codeword confidence metrics,need to be stored, not N×W values, because confidence applies tocodewords, or on a per-codeword basis, rather than to individual bits.

In cases where it is impractical to actually compare the error count, itis a reasonable approximation to use just two flags: “Uncorrectable” and“#errors=T”. Alternatively, the flags can be: maximum number ofcorrections done; and less than maximum number of corrections done.

Each parity bit is a member of two codewords: C_(a) and P_(b). Theseparity codewords are assembled, or calculated, in step 154 and aresimultaneously, in step 156, with the information codewords. The paritycodewords also use the confidence-based error mask reconciliation ofstep 158. The post-vote mask is applied to the data, and the data ispassed to the next stage.

The steps 152 to 158 are repeated in iterations 2 to S for allinformation codewords and corresponding party codewords in the receivedencoded message block. For example, additional BCH decode of allcodewords is performed. Each is identical to the first iteration, andworks on the output of the previous iteration. In one embodiment, valuesof S in the range of 6-10 are beneficial. This is equivalent to a 3-5stage decoder of I.4 or I.7 type, which have separate row and column ateach stage.

Reconciliation is iteratively performed after each BCH decode stage, inthe same way as for the first iteration. If no additional codewords arebeing corrected, or when the maximum available in the implementation isreached, iteration ceases.

Erasure Pattern Detection

If a limited number of codewords remain uncorrectable, then all theerrors must reside at the intersections of those codewords.

Erasure-decode techniques can be used to cover these cases.

The amount of erasure filling that can practically be done depends onthe ratio between T and the maximum number of bits overlapping betweenany two codewords. For K/2W<T, a set of three uncorrectable codewordsshould be correctable. In any event, only a small number oferasure-capable decoders are required.

In one embodiment, an apparatus for forward error correction isprovided, which performs the method shown in FIG. 8. The apparatus canbe implemented using standard logic gates and memories in an integratedcircuit, Field-programmable gate array, or similar technology (a‘hardware’ embodiment).

One embodiment of the present disclosure can be described as followsdescribing method steps in relation to associated hardware. A Framerblock (not shown) locates the Message Blocks within the received datastream, by using the framing information added in the step described inparagraph [0042]. These Message Blocks are presented at the input asshown in FIG. 8. The Codeword Assembly operation is performed using ahardware interleaver, which may be a programmable shift register writinginto one or more memory blocks. The Parity Codeword Assemblerreassembles the Parity Codewords by extracting the relevant bits fromthe incoming Message Block and writing them into a memory.

The BCH Decoders are implemented using the well-established techniquesof BCH decoding. The number of errors for each codeword may be loadedinto a shift register.

The Reconciliation step may be implemented by reading two rows at a timefrom the codeword array, and then implementing the comparator describedin Table 1 on a bitwise basis between the first (‘home’) row and thesecond (‘away’) row. The ‘away’ row bits and error counts can be linedup with the ‘home’ row using a programmable shift registers.

The ‘Done” decision box can be implemented using standard logic.Repetition of the steps can be done by looping back for multiple passeswithin the same hardware, or by passing the information to assubsequent, pipelined decoder stage. In either event, decoder stagesthat are not required may be placed into a low-power state.

The Erasure decoding step can be implemented by counting the number ofuncorrectable blocks reported by the final stage. Techniques for erasuredecode of BCH are well described in the prior art.

In other embodiments, the method in FIG. 8 may be implemented usingsoftware instructions executed in a microprocessor, or a blend of‘hardware’ and software.

While particular embodiments have been described above, otherembodiments are described below.

The parameter values (M, N, K, T, W) are variable and may be chosendifferently depending on the desired application.

Swizzle codes can be built with other interleaving schemes other thanthe one described. For instance the rotational multiple R can be greaterthan one, so long as R and W−1 are relatively prime. The interleavingscheme described is beneficial, in that it allows for minimal-latencyencoding and decoding using a simple programmable shift register.

Block codes other than BCH can be used to build a swizzle code.

The degree of erasure filling can be increased by using variouspublished techniques.

The FEC protecting the Parity Array can have different parameters (oreven be a different code type) from the base component code. Adjustmentsmay be required to the error mask reconciliation in this case, tomaintain an effective confidence comparison. These adjustments will beapparent to one of ordinary skill in the art.

The value of T can be varied between different codewords to achieve aconvenient rate, instead of shortening the codewords.

The number of stages required to decode a block can be varied based onthe number and pattern of bit errors in that block. The maximum numberdesirable is considerably in excess of the average. To reduce the sizeof the implementation, the FEC can be provisioned with slightly morethan the average number of stages required. Each block is decodediteratively until no more progress is being made. An elastic FIFO isprovided to buffer incoming blocks during periods where the decoder isdoing many iterations and thus cannot meet line rate. When the FIFObecomes full, the decoder is forced to stop iterating and begin workingon new blocks.

FIG. 9 is a graph illustrating performance of an FEC according to anembodiment of the present disclosure. At 1E-8, this FEC has beensimulated to improve coding gain by 0.4 dB over I.7, and by 0.6 dB overI.4, in the presence of an AWGN channel followed by a hard-decisionslicer. In another embodiment, this performance can be provided down to1E-13.

The total decode latency of this code is implementation dependant.However, the 2-stage decoder can be implemented with latency under 12us, and the 10-stage one with latency under 60 us.

The total decode latency of this code is implementation dependant.However, the 2-stage decoder with parameters N-1761, T=5, W=352 can beimplemented with latency under 12 us, and the 10-stage one with latencyunder 60 us for an 111.8 Gbps system.

In the preceding description, for purposes of explanation, numerousdetails are set forth in order to provide a thorough understanding ofthe embodiments. However, it will be apparent to one skilled in the artthat these specific details are not required in order to practice theembodiments. In other instances, well-known electrical structures andcircuits are shown in block diagram form in order not to obscure thesubject matter. For example, specific details are not provided as towhether the embodiments of the disclosure described herein areimplemented as a software routine, hardware circuit, firmware, or acombination thereof.

Embodiments of the disclosure can be represented as a software productstored in a machine-readable medium (also referred to as acomputer-readable medium, a processor-readable medium, or a computerusable medium having a computer-readable program code embodied therein).The machine-readable medium can be any suitable tangible medium,including magnetic, optical, or electrical storage medium including adiskette, compact disk read only memory (CD-ROM), memory device(volatile or non-volatile), or similar storage mechanism. Themachine-readable medium can contain various sets of instructions, codesequences, configuration information, or other data, which, whenexecuted, cause a processor to perform steps in a method according to anembodiment of the disclosure. Those of ordinary skill in the art willappreciate that other instructions and operations necessary to implementthe described disclosure can also be stored on the machine-readablemedium. Software running from the machine-readable medium can interfacewith circuitry to perform the described tasks.

Embodiments of the disclosure can be represented as a hardware productimplemented in an Integrated Circuit (IC), Programmable Gate Array, orsome combination of Integrated Circuit(s), Programmable Gate Array(s),and Software. Those of ordinary skill in the art will appreciate thatother functions can also be implemented on such Integrated Circuits orProgrammable Gate Arrays.

The above-described embodiments are intended to be examples only.Alterations, modifications and variations can be effected to theparticular embodiments by those of skill in the art without departingfrom the scope of the disclosure, which is defined solely by the claimsappended hereto.

1. A method of assembling a codeword in a forward error correctionsystem having K information bits in a total of N bits, the methodcomprising: obtaining K/2 home column information bits from a homecolumn of an information bit array; obtaining K/2 away columninformation bits from a selected number of away columns of theinformation bit array, the selected number of away columns consisting ofinformation bit array columns other than the home column; combining theK/2 home column information bits with the K/2 away column informationbits to assemble K information bits; calculating N−K redundant paritybits associated with the assembled K information bits according to anerror control code; and appending the N−K redundant parity bits to theassembled K information bits to assemble the codeword valid under theerror control code.
 2. The method of claim 1, further comprisingprepending padding bits to the assembled K information bits.
 3. Themethod of claim 1, wherein the K/2 home column information bits and theK/2 away column information bits are combined in an alternating mannerto assemble the K information bits.
 4. The method of claim 1 whereinobtaining the K/2 away column information bits comprises following adiagonal progression through the selected number of away columns thatskips the home column.
 5. The method of claim 1 wherein obtaining theK/2 away column information bits comprises following a diagonalprogression through the selected number of away columns that skips thehome column and one or more columns adjacent to the home column.
 6. Themethod of claim 1 wherein obtaining the K/2 away column information bitsbegins at a first away column adjacent the home column.
 7. The method ofclaim 1 wherein combining the K/2 home column information bits and theK/2 away column information bits comprises interleaving the K/2 homecolumn information bits and the K/2 away column information bits toassemble the K information bits.
 8. The method of claim 1 wherein theerror control code is a BCH (Bose, Chaudhuri, and Hocquenghem) code. 9.An encoder comprising: an information bit array assembly module forassembling information bits into an information bit array; and acodeword assembly module for assembling a codeword in a forward errorcorrection system having K information bits in a total on N bits by:obtaining K/2 home column information bits form a home column of theinformation bit array; obtaining K/2 away column information bits from aselected number of away columns of the information bit array, the awaycolumns consisting of information bit array columns other than the homecolumn; and, combining the K/2 home column information bits with the K/2away column information bits to assemble K information bits; calculatingN−K redundant parity bits associated with the assembled K informationbits according to an error control code; and appending the N−K redundantparity bits to the assembled K information bits to assemble the codewordvalid under the error control code.
 10. The encoder of claim 9, whereinthe codeword assembly module prepends padding bits to the assembled Kinformation bits.
 11. The encoder of claim 9, wherein the Error ControlCode is a BCH (Bose, Chaudhuri, and Hocquenghem) code.
 12. The encoderof claim 9, wherein the K/2 home column information bits and the K/2away column information bits are combined in an alternating manner toassemble the K information bits.
 13. The encoder of claim 9, wherein thecodeword assembly module comprises a plurality of programmable shiftregisters to store the information bits during assembly of the codeword.14. The encoder of claim 13, wherein the plurality of programmable shiftregisters interleave the K/2 home column information bits and the K/2away column information bits to assemble the K information bits.
 15. Theencoder of claim 9, further comprising: a codeword array assembly modulefor assembling a plurality of codewords associated with the informationbits into an information codeword array.
 16. The encoder of claim 15,further comprising: a parity bit array assembly module for assemblingthe N−K redundant parity bits into a parity bit array; and a paritycodeword array assembly module for assembling a plurality of paritycodewords associated with the information bits into a parity codewordarray.
 17. The encoder of claim 16, further comprising: a parity onparity array assembly module for assembling parity on parity bits into aparity on parity bit array, the parity on parity bits being associatedwith the N−K redundant parity bits.
 18. The encoder of claim 17, furthercomprising: a framing module for combing the information codeword array,the parity codeword array, and the parity on parity array into anencoded message block.